Semiconductor memory device

ABSTRACT

The present invention for preventing a data error by satisfying specifications of tHD and tCBPH is provided. The semiconductor memory device having an enough margin for a write/read operation includes a pre-charging block for performing a pre-charging operation based on a chip selection control signal; a write/read strobe generating block for performing a write/read operation based on the chip selection control signal and a chip selection signal; and a chip selection buffering block for generating the chip selection control signal based on the chip selection signal to control a timing of the pre-charging operation and a timing of the write/read operation.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device; and,more particularly, to a semiconductor memory device, which can prevent adata error generally occurring due to an enabling timing of a chipselection signal in a pseudo static random access memory device.

DESCRIPTION OF THE RELATED ART

Generally, dynamic random access memory (DRAM) devices store informationinto capacitors in the form of charges. The stored charges of thecapacitors are distributed to corresponding bit lines throughtransistors, and sense amplifiers amplify voltages to read data. Since amemory cell includes one transistor and one capacitor, a memory devicewith large capacitance can be implemented in a smaller area.

Memory devices have currently been scaled down to achieve severalintended functions such as high operation speed, decreased powerconsumption and minimized processing systems. As memory devices havebeen minimized, the capacitor areas of the memory cells have beenreduced, resulting in a decreased capacitance level. Due to thedecreased capacitance level, an amount of charges that can be retainedis reduced even if data are inputted at the same voltage level withrespect to the capacitors.

A refresh operation is generally performed periodically to compensatethe decreased amount of charges of the capacitors that can be retained.The refresh operation reads data stored into the capacitors of thememory cells through employing bit lines and then, the read data areamplified by sense amplifiers. The amplified data are rewritten onto thecapacitors of the original memory cells.

Therefore, if a data retention characteristic is degraded in micronizeddevices, it is often required to shorten a period of the refreshoperation to compensate the degradation of the data retentioncharacteristic. However, if the refresh operation period is shortened,external processing devices cannot access DRAM devices during therefresh operation and thus, the processing systems may perform poorly.

Also, if the period of the refresh operation is shortened, current forthe refresh operation may be consumed more highly. Particularly, it maybe difficult to satisfy a low level of standby current required for adata retention mode in portable devices that operate by batteries. Thus,DRAM devices cannot be applied to those portable devices requiring lowpower consumption.

As one method of resolving the above limitation, a pseudo static randomaccess memory (PSRAM) device has been introduced. The PSRAM deviceoperates similarly to a static random access memory (SRAM) device. Inthe PSRAM device, among memory access cycles, a cycle of a readoperation and a write operation and a cycle of a refresh operation runconsecutively. That is, since the refresh operation is executed withinone memory access cycle, it is possible to hide the refresh operationwith respect to an external access operation, and thus, a DRAM devicecan operate as a SRAM device.

FIG. 1 is a timing diagram showing an operation of a conventional PSRAMdevice for controlling a chip selection signal.

A period from a rising edge of a clock CLK to a rising edge of a chipselection signal CSB is called ‘tHD’. However, the conventional PSRAMdevice has a high value of a tHD specification. That is, the chipselection signal CSB is disabled at the next clock CLK after the lastdata d3 is inputted. However, the conventional tHD specification cannotsatisfy the minimum period of 2 ns.

In the conventional tHD specification, after the tHD period, the chipselection signal CSB is enabled immediately as a period of ‘tCBPH’representing a width of a high pulse of the chip selection signal CSB ispassed by. Herein, the tCBPH period is generally 5 ns. If the chipselection signal CSB is enabled immediately after the state that the tHDperiod is passed by and the tCBPH period is satisfied, the chipselection signal CSB is specifically set to be enabled before a risingedge of the next clock CLK. Therefore, when the tHD period is 2 ns, itmay be difficult to write the data d3, which is inputted as beingsynchronized with the clock CLK, on a memory cell.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide asemiconductor memory device, which can prevent a data error bysatisfying specifications of tHD and tCBPH and writing a lastly inputteddata at a tHD interval on a memory cell of a synchronous pseudo staticrandom access memory (PSRAM) device.

In accordance with an aspect of the present invention, there is provideda semiconductor memory device, including a pre-charging block forperforming a pre-charging operation based on a chip selection controlsignal; a write/read strobe generating block for performing a write/readoperation based on the chip selection control signal and a chipselection signal; and a chip selection buffering block for generatingthe chip selection control signal based on the chip selection signal tocontrol a timing of the pre-charging operation and a timing of thewrite/read operation.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome apparent from the following description of the preferredembodiments given in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a timing diagram illustrating an operation of a conventionalsemiconductor memory device;

FIG. 2 is a configuration diagram illustrating a semiconductor device inaccordance with an embodiment of the present invention;

FIG. 3 is a detailed circuit diagram of a clock buffering blockillustrated in FIG. 2;

FIG. 4 is a detailed circuit diagram of a first pulse generating unitillustrated in FIG. 3;

FIG. 5 is a detailed circuit diagram of a chip selection buffering blockillustrated in FIG. 2;

FIGS. 6 and 7 are waveform diagrams of exemplary operations of the chipselection buffering block illustrated in FIG. 5;

FIG. 8 is a detailed circuit diagram of a page controlling blockillustrated in FIG. 2; and

FIG. 9 is a detailed circuit diagram of a write/read strobe generatingblock illustrated in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor memory device in accordance with exemplary embodimentsof the present invention will be described in detail with reference tothe accompanying drawings.

FIG. 2 is a configuration diagram of a semiconductor memory device inaccordance with an embodiment of the present invention.

The semiconductor memory device includes a clock buffering block 100, achip selection buffering block 200, a pre-charging block 300, a pagecontrolling block 400, and a write/read strobe generating block 500.

The clock buffering block 100 buffers a clock CLK and generates a clocktransition detection signal CTDB for every rising edge of the clock CLK.The chip selection buffering block 200 buffers a power-up signal PWRUP,the clock transition detection signal CTDB and a chip selection signalCSB and outputs a chip selection controlling signal CSB4 for determininga pre-charge operation of a word line. The pre-charging block 300controls a pre-charge operation according to the chip selection controlsignal CSB4.

The page buffering block 400 controls a page address according to thechip selection signal CSB, an address transition control signal ADVB andthe power-up signal PWRUP and outputs a write/read strobe control signalWR_STB_C. The write/read strobe generating block 500 controls a strobeoperation according to the chip selection control signal CSB4, the clocktransition detection signal CTDB and the write/read strobe controlsignal WR_STB_C and outputs a write/read strobe signal WR_STB.

FIG. 3 is a detailed circuit diagram of the clock buffering block 100illustrated in FIG. 2.

The clock buffering block 100 includes first to fourth inverters IV1 toIV4, and a first pulse generating unit 110. The first inverter IV1 andthe second inverter IV2 delay the clock CLK without an inversion andoutput an input signal IN. The first pulse generating unit 110 outputsan output signal OUT with a certain pulse width according to the inputsignal IN. The third inverter IV3 and the fourth inverter IV4 delay theoutput signal OUT without an inversion and output the clock transitiondetection signal CTDB. On the basis of these sequential steps, the clockbuffering block 100 generates the clock transition detection signal CTDBfor every rising edge of the clock CLK.

FIG. 4 is a detailed circuit diagram of the first pulse generating unitillustrated in FIG. 3.

The first pulse generating unit 110 includes fifth to ninth invertersIV5 to IV9 and a first NAND gate ND1. The fifth to the ninth invertersIV5 to IV9 delay the input signal IN with an inversion. The first NANDgate ND1 performs a NAND operation on the input signal IN and an outputsignal of the ninth inverter IV9 and outputs the output signal OUT withthe certain pulse width. Hence, the first pulse generating unit 110outputs the output signal OUT of a low pulse when the input signal IN istransited from a low level to a high level.

FIG. 5 is a detailed circuit diagram of the chip selection bufferingblock illustrated in FIG. 2.

The chip selection buffering block 200 includes tenth to thirteenthinverters IV10 to IV30, a second pulse generating unit 220, a firstP-channel metal oxide semiconductor (PMOS) transistor, P1, a firstN-channel metal oxide semiconductor (NMOS) transistor N1, and a secondNMOS transistor N2, and second to fourth NAND gates ND2 to ND4.

The tenth inverter IV10 and the eleventh inverter IV11 delay the chipselection signal CSB. The twelfth inverter IV12 inverts an output of theeleventh inverter IV11. A first delaying unit 210 includes thethirteenth to sixteenth inverters IV13 to IV16 and delay an output ofthe twelfth inverter IV12 for a predetermined time. The second pulsegenerating unit 220 generates a signal with a certain pulse widthaccording to an output of the first delaying unit 210. A second delayingunit 230 including the eighteenth inverter IV18 to the twenty-firstinverter IV21 and a third delaying unit 240 including the twenty-secondinverter IV22 to the twenty-fifth inverter IV25 delay the output of theeleventh inverter IV11 for a predetermined time and transmits the outputto a first node B.

The first PMOS transistor P1 is connected between a power supplyterminal and a second node A and is supplied with the clock transitiondetection signal CTDB through a gate. The first NMOS transistor N1 isconnected between the first node A and a ground voltage terminal and issupplied with an output of the seventeenth inverter IV17 through a gate.The twenty-seventh inverter IV27 and the twenty-eighth inverter IV28serve as a latching unit, which latches an output of the second node A.The second NMOS transistor N2 is connected between the second node A anda ground voltage terminal and is supplied with the power-up signal PWRUPthrough a gate, wherein the power-up signal PWRUP is inverted by thetwenty-sixth inverter IV26.

The second NAND gate ND2 performs a NAND operation to the output of thefirst node B and the output of the eleventh inverter IV11 and outputsthe NAND operation result to a third node C. The third NAND gate ND3performs a NAND operation to an output of the twenty-ninth inverter IV29and an output of the third node C and outputs the NAND operation resultto a fourth node D. The fourth NAND gate ND4 performs a NAND operationto an output of the fourth node D and the output of the eleventhinverter IV11. The thirtieth inverter IV30 inverts an output of theforth NAND gate ND4 and outputs the chip selection control signal CSB4.

FIG. 6 is a waveform diagram illustrating an operation of the chipselection buffering block 200 when a tCBPH period is shorter than onecycle of the clock CLK. FIG. 7 is a waveform diagram illustrating anoperation of the chip selection buffering block 200 when a tCBPH periodis longer than one cycle of the clock CLK.

As illustrated in FIG. 6, when the chip selection signal CSB at thetCBPH period with a narrow pulse width is inputted from a pad, the chipselection control signal CSB4 retains a low level. The pre-chargeoperation is not carried out by continuously retaining the low level ofthe chip selection control signal CSB4. Hence, it is possible to write adata, which is inputted lastly during an interval of tHD, on a memorycell.

On the other hand, as illustrated in FIG. 7, the chip selection signalCSB at a tCBPH period with a wide pulse width is inputted from a pad,the chip selection control signal CSB4 is in a high level. As the chipselection control signal CSB4 is transited from a low level to a highlevel, the pre-charge operation that disables a currently enabled wordline is carried out to terminate a write/read operation. That is, sincethe chip selection control signal CSB4 retains the high level due to acertain delay time, the pre-charge operation with respect to the wordline is carried out after the last input data is written on the memorycell.

FIG. 8 is a detailed circuit diagram of the page controlling block 400illustrated in FIG. 2.

The page controlling block 400 includes thirty-first to forty-firstinverters IV31 to IV41, a third pulse generating unit 410, a fourthpulse generating 430, a fourth delaying unit 420, a second PMOStransistor P2, third and fourth NMOS transistors N3 and N4, a pagecontrol signal generating unit 440, and a first NOR gate NOR1.

The thirty-first to thirty-third inverters IV31, IV32 and IV33 invertand delay the address transition control signal ADVB and, output theinverted address transition control signal. The third pulse generatingunit 4010 outputs a signal with a certain width according to theinverted address transition control signal ADV. The fourth delaying unit420 delays the chip selection signal CSB without an inversion. Thefourth pulse generating unit 430 delays an output of the fourth delayingunit 420 and outputs a signal with a certain width.

The second PMOS transistor P2 and the third NMOS transistor N3 areconnected between a power supply terminal and a ground voltage terminal.The second PMOS transistor P2 is supplied with an output of the thirdpulse generating unit 410 through a gate. The third NMOS transistor N3is supplied with an output of the third eighth inverter IV38 through agate.

The fortieth inverter IV40 and the forty-first inverter IV41 serving asa latching unit latch an output of the second PMOS transistor P2 andoutput another chip selection control signal CS_CON. The fourth NMOStransistor N4 is connected in parallel with the third NMOS transistorN3, and the power-up signal PWRUP inverted by the thirty-ninth inverterIV39 is inputted to the fourth NMOS transistor N4 through a gate.

The page control signal generating unit 440 generates a page controlsignal P_CON for controlling a page operation according to the addresstransition control signal ADV. The first NOR gate NOR1 performs a NORoperation to the other chip selection control signal CS_CON and the pagecontrol signal P_CON and outputs the write/read strobe control signalWR_STB_C.

FIG. 9 is a detailed circuit diagram of the write/read strobe generatingblock 500 illustrated in FIG. 2.

The write/read strobe generating block 500 includes forty-second toforty-eighth inverters IV42 to IV48, a fifth NAND gate ND5, and a secondNOR gate NOR2. The forty-second inverter to forty-seventh to invertersIV42 to IV47 delay the chip selection control signal CSB4 for apredetermined time. The second NOR gate NOR2 performs a NOR operation toan output of the forty-seventh inverter IV47 and the clock transitiondetection signal CTDB. The fifth NAND gate ND5 performs a NAND operationto the write/read strobe control signal WR_STB_C and an output the NORgate NOR2. The forty-eighth inverter IV48 inverts an output of the fifthNAND gate ND5 and outputs the write/read strobe signal WR_STB.

Hereinafter, operation of the semiconductor memory device (i.e., thePSRAM device) configured as above will be described in detail.

The power-up signal PWRUP is transited from a low level to a high levelwhile the PSRAM device is supplied with the initial power. At this time,values of internal latch circuits are determined. Thus, the second nodeA of the chip selection buffering block 200 latches a low levelaccording to the power-up signal PWRUP.

If the PSRAM device operates asynchronously, the clock CLK is nottoggled and thus the clock transition detection signal CTDB retains ahigh level continuously. As a result, the second node A is in a lowlevel because of the power-up signal PWRUP and the fourth node D is in ahigh level, so that the chip selection control signal CSB4 becomesidentical to a signal inputted to a chip selection signal CSB pad.

On the other hand, in the case of a synchronous PSRAM device, the inputof the chip selection signal CSB satisfies the tHD specification betweenrising edges of the clock CLK. As illustrated in FIG. 6, operation ofthe PSRAM device when the tCBPH period is shorter than one cycle of theclock CLK will be described hereinafter.

When the clock CLK is transited from a low level to a high level, theclock buffering block 100 generates the clock transition detectionsignal CTDB, which is a low pulse, for every rising edge of the clockCLK. An output of the second pulse generating unit 220 is in a low levelwhen the chip selection signal CSB is enabled in a low level.

As a result, the second node A latches a signal in a low level by thetwenty-seventh inverter IV27 and the twenty-eighth inverter IV28 (i.e.,the latching unit) and then latches a signal in a high level when theclock transition detection signal CTDB is inputted in a low level at therising edge of the clock CLK.

The first node B is inputted with a signal obtained as the seconddelaying unit 230 and the third delaying unit 240 delay the chipselection signal CSB. That is, as illustrated in FIG. 6, when the chipselection signal CSB at the tCBPH period with the pulse width shorterthan the delay time of the first node B is inputted from the pad, thechip selection signal CSB is in a low level as passing through thesecond NAND gate ND2 to the fourth NAND gate ND4. Hence, the chipselection control signal CSB4 retains a low level.

As the chip selection control signal CSB4 retains the low level, thepre-charging block 300 does not pre-charge a word line. Therefore, thelastly inputted data during the tHD interval can be written on a memorycell.

As illustrated in FIG. 7, when the chip selection signal CSB at thetCBPH period with the pulse width larger than the delay time of thefirst node B is inputted from the pad, the chip selection control signalCSB4 is transited to a high level and enabled in a low level again.

There is a predetermined delay time before the chip selection controlsignal CSB4 is transited to the high level. Thus, a data inputted at thetHD interval can be written on a memory cell for the predetermined delaytime of the chip selection control signal CSB4. Next, when the chipselection control signal CSB4 is transited from a low level to a highlevel, the pre-charging block 300 performs a pre-charge operation thatdisables a currently enabled word line, thereby terminating thewrite/read operation.

Herein, the pre-charging block 300 disables the word line after thewrite/read operation is terminated. In accordance with the embodiment ofthe present invention, the pre-charge operation is set to be carried outwhen the chip selection control signal CSB4 is disabled.

The address transition control signal ADVB of the page controlling block400 is synchronized with the clock CLK at the moment that an externalinstruction is inputted to the synchronous PSRAM device, whereby theaddress transition control signal ADVB is in a low level. Therefore, thepage control signal generating unit 400 generates the page controlsignal P_CON at the moment that among the synchronous write/readoperations, the write/read strobe signal WR_STB is enabled according tothe address transition control signal ADVB.

When the address transition control signal ADVB is in a low level as anexternal instruction is inputted, the inverted address control signalADV is in a high level and the output of the third pulse generating 410is in a low level. As a result, the chip selection control signal CS_CONof a low level is latched. Under this state, the write/read strobecontrol signal WR_STB_C is outputted according to the page controlsignal P_CON.

At this time, if the chip selection signal CSB is in a high level, it isunnecessary to generate the write/read strobe signal WR_STB. Therefore,when the chip selection signal CSB is in a high level, the chipselection control signal CS_CON of a high level is latched to therebyprevent a generation of the write/read strobe signal WR_STB.

Meanwhile, at the write/read strobe generating block 500, when the chipselection control signal CSB4 is in a low level as the PSRAM device isenabled, the clock CLK is toggled, whereby the clock transitiondetection signal CTDB is continuously inputted in a low level. At thistime, when the write/read strobe control signal WR_STB_C is inputted ina high level, the write/read strobe signal WR_STB is enabled in a highlevel for every clock, so that the PSRAM device can carry out thewrite/read operation.

In accordance with the embodiment of the present invention, thewrite/read strobe signal WR_STB necessary for the pre-charge operationand the write/read operation is controlled by the chip selection controlsignal CSB4 generated at the chip selection buffering block 200 in orderfor a data inputted at the tHD interval to be written on a memory cell.Thus, when the chip selection signal CSB having a low value of the tCBPHperiod is disabled right after the tHD period, the pre-charge operationfor disabling a currently enabled word line is not carried out. Afterthe tHD period, if the chip selection signal CSB is disabled, thewrite/read strobe signal WR_STB is generated to write a data on a memorycell.

Also, after the tHD period, if the chip selection signal CSB with a highvalue of the tCBPH period is inputted, the chip selection control signalCSB4 is disabled after a predetermined delay time. On the basis of thechip selection control signal CSB4, the word line is pre-charged towrite a data, which is inputted lastly during the tHD period, on amemory cell.

On the basis of the embodiment of the present invention, it is possibleto prevent a generation of a data error caused by a certain timing of achip selection signal. The present application contains subject matterrelated to the Korean patent application No. KR 2005-0058496, filed inthe Korean Patent Office on Jun. 30, 2005, the entire contents of whichbeing incorporated herein by reference.

While the present invention has been described with respect to theparticular embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the scope of the invention as defined in the following claims.

1. A semiconductor memory device having an enough margin for awrite/read operation, comprising: a pre-charging block for performing apre-charging operation based on a chip selection control signal; awrite/read strobe generating block for performing a write/read operationbased on the chip selection control signal and a chip selection signal;and a chip selection buffering block for generating the chip selectioncontrol signal based on the chip selection signal to control a timing ofthe pre-charging operation and a timing of the write/read operation. 2.The semiconductor memory device of claim 1, wherein the chip selectioncontrol signal is determined according to a period (tHD) from a risingedge of a clock to a rising edge of a chip selection signal and a highpulse retention period (tCBPH) of the chip selection signal by receivinga clock transition detection signal and the chip selection signal. 3.The semiconductor memory device of claim 2, wherein the write/readstrobe generating block performs the write/read operation according tothe chip selection control signal, a write/read strobe control signaland the clock transition detection.
 4. The semiconductor memory deviceof claim 3, further comprising: a clock buffering block for bufferingthe clock to output the clock transition detection signal to the chipselection buffering block and the write/read strobe generating block inevery rising edge of the clock; and a page controlling block outputtingthe write/read strobe control signal to the write/read strobe generatingblock for controlling the write/read operation according to the chipselection signal and an address transition control signal.
 5. Thesemiconductor memory device of claim 4, wherein the page controllingblock disables the write/read strobe control signal when the chipselection signal is disabled.
 6. The semiconductor memory device ofclaim 4, wherein the page controlling block includes: a first pulsegenerating unit delaying the address transition control signal andgenerating a signal with a predetermined pulse width; a second pulsegenerating unit delaying the chip selection signal and generating asignal with a predetermined pulse width; a first voltage operating unitoutputting a power voltage or a ground voltage according to an outputfrom the first pulse generating unit and an output from the second pulsegenerating unit; a first latching unit latching an output from the firstvoltage operating unit and outputting another chip selection controlsignal; a first operating unit pre-charging an output terminal of thefirst voltage operating unit according to a power-up signal; a pagecontrol signal generating unit outputting a page control signalcontrolling a page operation according to the inverted addresstransition control signal; and a first logic operation unit performing alogic operation to the other chip selection control signal and the pagecontrol signal and outputting the write/read strobe control signal. 7.The semiconductor memory device of claim 6, wherein the first logicoperation unit controls the write/read strobe control signal accordingto the page control signal as the chip selection control signal is in alow level when the address transition control signal is enabled.
 8. Thesemiconductor memory device of claim 3, wherein the chip selectionbuffering block controls: the pre-charge operation to be performed atthe next clock by retaining the chip selection control signal in a lowlevel when the high pulse retention period is shorter than one cycle ofthe clock; and the pre-charge operation to be performed after apredetermined delay time by transiting the chip selection control signalto a high level when the high pulse retention period is longer than onecycle of the clock.
 9. The semiconductor memory device of claim 4,wherein the chip selection buffering block controls: the pre-chargeoperation to be performed at the next clock by retaining the chipselection control signal in a low level when the high pulse retentionperiod is shorter than one cycle of the clock; and the pre-chargeoperation to be performed after a predetermined delay time by transitingthe chip selection control signal to a high level when the high pulseretention period is longer than one cycle of the clock.
 10. Thesemiconductor memory device of claim 3, wherein the chip selectionbuffering block includes: a third pulse generating unit delaying thechip selection signal and outputting a signal with a predetermined pulsewidth to a first node; a plurality of delaying units delaying the chipselection signal for a predetermined time and outputting the chipselection signal to a second node; a second voltage operating unitcontrolling a voltage level of the fist node according to an output fromthe third pulse generating unit and the clock transition detectionsignal; a second latching unit latching an output of the first node; asecond operating unit pre-charging the first node according to thepower-up signal; and a second logic operation unit performing a logicoperation to an output from the second latching unit, an output from thesecond node and the chip selection signal and outputting the chipselection control signal.
 11. The semiconductor memory device of claim4, wherein the chip selection buffering block includes: a third pulsegenerating unit delaying the chip selection signal and outputting asignal with a predetermined pulse width to a first node; a plurality ofdelaying units delaying the chip selection signal for a predeterminedtime and outputting the chip selection signal to a second node; a secondvoltage operating unit controlling a voltage level of the fist nodeaccording to an output from the third pulse generating unit and theclock transition detection signal; a second latching unit latching anoutput of the first node; a second operating unit pre-charging the firstnode according to the power-up signal; and a second logic operation unitperforming a logic operation to an output from the second latching unit,an output from the second node and the chip selection signal andoutputting the chip selection control signal.
 12. The semiconductormemory device of claim 3, wherein the write/read strobe generating blockincludes: a third logic operation unit performing a logic operation tothe chip selection control signal delayed for a predetermined time andthe clock transition detection signal; a fourth logic operation unitperforming a logic operation to the write/read strobe control signal andan output from the third logic operation unit; and an inverter invertingan output from the fourth logic operation unit and outputting thewrite/read strobe signal.
 13. The semiconductor memory device of claim4, wherein the write/read strobe generating block includes: a thirdlogic operation unit performing a logic operation to the chip selectioncontrol signal delayed for a predetermined time and the clock transitiondetection signal; a fourth logic operation unit performing a logicoperation to the write/read strobe control signal and an output from thethird logic operation unit; and an inverter inverting an output from thefourth logic operation unit and outputting the write/read strobe signal.14. The semiconductor memory device of claim 12, wherein the third logicoperation unit is a NOR gate.
 15. The semiconductor memory device ofclaim 12, wherein the fourth logic operation unit is a NAND gate. 16.The semiconductor memory device of claim 13, wherein the third logicoperation unit is a NOR gate.
 17. The semiconductor memory device ofclaim 13, wherein the fourth logic operation unit is a NAND gate.